As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFETs have been pursued as a potential device option for continued CMOS scaling.
Bottom and top spacers offset the bottom and top source/drains, respectively, from the VFET gate. However, the processes typically employed to define the top spacer depend on the dimensions at the top of the fin (which can vary from fin-to-fin due to process variations), thus making the thickness of the top spacer extremely hard to control. Variations in the top spacer thickness can undesirably lead to a higher risk of gate to source/drain short, reliability concerns due to breakdown, variation of the gate to source/drain capacitance, as well as make it difficult to set the junction to be close to the gated region.
Therefore, improved VFET fabrication techniques that control a thickness of the top spacer would be desirable.